| 摘要 |
An Encryption processor is disclosed comprising an S-box unit, a byte permutation unit, a MixColumns unit and a key expansion unit. In an embodiment the byte permutation unit comprises a data input terminal for receiving input data, two or more row processors, each row processor having an input coupled to the input terminal and an output, and a clock gating circuit for generating for each of the two or more row processors a gated clock signal. Furthermore, a clock gated key expansion unit is disclosed. By clock gating, the power consumption of the processor is reduced which extends the battery life time in battery powered devices.
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