| 摘要 |
A system comprises a control unit and a circuit. The circuit comprises an input clock connection for receiving a clock signal from the control unit, a first output clock connection for providing the clock signal to a first memory unit, a second output clock connection for providing the clock signal to a second memory unit, a control connection for receiving a control signal from the control unit. The circuit further comprises multiplexer circuitry connected to the input clock connection, the first and the second clock connections and the control connection. The multiplexer circuitry is configured to react to the control signal from the control unit by providing the clock signal to the first memory unit or the second memory unit. In other words, a clock signal is multiplexed in such a way that only one memory unit at a time receives the clock signal. An effect of this is that in a system having two or more memory units, unique access is provided to one memory unit at a time.
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