发明名称 |
CLOCK CONTROL DEVICE, CLOCK CONTROL METHOD, CLOCK CONTROL PROGRAM AND INTEGRATED CIRCUIT |
摘要 |
An instruction detecting section (235) detects whether or not there is any succeeding instruction executable regardless of an order based on a data dependency relationship between a presently executed instruction and a succeeding instruction following the presently executed instruction. A clock switch judging section (236) receives notification of the start and end of a memory stall, determines whether or not a memory stall is occurring, and judges whether to switch a clock signal to be supplied to a CPU (200) to a low clock signal (239) or to stop the clock signal based on a detection result of the instruction detecting section (235) if it is judged that the memory stall is occurring. A clock switching section (237) switches the clock signal based on judgment by the clock switch judging section (236). By this construction, power consumption can be reduced without reducing performance.
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申请公布号 |
US2010325469(A1) |
申请公布日期 |
2010.12.23 |
申请号 |
US20080526365 |
申请日期 |
2008.12.10 |
申请人 |
YOKOYAMA RYO;TANIKAWA TADAO |
发明人 |
YOKOYAMA RYO;TANIKAWA TADAO |
分类号 |
G06F9/30;G06F1/04 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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