A bus system comprising a master connected to one or more slave devices via a bus is disclosed. The bus system is able to effectively communicate control information during a calibration phase and to individually determine appropriate timing and/or voltage offsets for each slave device. The offsets are used to optimise transfer timing (including duty cycle characteristics), signal equalization, and voltage levels for data exchanged between the master and the slave devices.
申请公布号
EP2264612(A2)
申请公布日期
2010.12.22
申请号
EP20100177780
申请日期
2000.10.12
申请人
RAMBUS INC.
发明人
ZERBE, JARED LEVAN;DONELLY, KEVIN S.;SIDIROPOULOS, STEFANOS;STARK, DONALD C.;HOROWITZ, MARK A.;YU, LEUNG;VU, ROXANNE;KIM, JUN;GARLEPP, BRUNO W.;HO, TSYR-CHYANG;LAU, BENEDICT CHUNG-KWONG