| 摘要 |
<p>A shared resource multi-thread array processor consists of an array of heterogeneous function blocks 107, 108 which are interconnected via a self-routing switch fabric 700. Processing of threads involves mapping individual instructions or groups of instructions to function blocks with corresponding functionality. Independent threads are allowed to share each functional block so as to optimally utilize the array resources. The output data from a function block is formatted into a token by appending a routing tag thereto; this token is then routed via the switch fabric to a thread coordinator 600 or the next function block in a thread sequence. Tokens from different threads are passed to the various addressable function blocks in a predefined sequence in order to implement the desired function. Each switch output port comprises a FIFO style memory that implements a plurality of separate queues. The separate port queues allows data from different threads to share the same hardware resources and the reconfiguration of switch fabric addresses further enables the formation of different data paths allowing the array to be configured for use in various applications. The array can be configured to implement parallel processing architectures such as Single Instruction Multiple Data (SIMD) and Multiple Instruction Multiple Data (MIMD).</p> |
