发明名称 |
LOOP TYPE CLOCK ADJUSTMENT CIRCUIT AND TEST DEVICE |
摘要 |
<p>A variable delay circuit applies a variable delay that corresponds to an analog signal to a reference clock so as to generate a delayed clock. A phase detection unit detects the phase difference between the delayed clock and the reference clock, and generates a phase difference signal having a level that corresponds to the phase difference. A counter performs a counting up operation or a counting down operation according to the level of the phase difference signal. A digital/analog converter converts the count value of the counter into an analog signal, and supplies the count value thus converted to the variable delay circuit. The counter comprises: a first counter configured to use a first thermometer code to count the lower group of digits of the count value according to the phase difference signal; a second counter configured to use a second thermometer code to count an upper group of digits of the count value according to the phase difference signal; and a control circuit configured to perform a control operation such that the Hamming distance is maintained at 1 even in a carry operation and a borrow operation of the first counter and the second counter.</p> |
申请公布号 |
KR20100133480(A) |
申请公布日期 |
2010.12.21 |
申请号 |
KR20107025369 |
申请日期 |
2009.04.07 |
申请人 |
ADVANTEST CORPORATION |
发明人 |
FUJITA KAZUHIRO;YAMAMOTO KAZUHIRO;SUDA MASAKATSU |
分类号 |
H03L7/081;H03K5/135;H03K5/26;H03K23/66;H03L7/06;H03L7/093 |
主分类号 |
H03L7/081 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|