| 摘要 |
The code generation apparatus includes: a clock generator which generates a clock signal of a first frequency; a timing controller which generates a timing signal of a second frequency lower than the first frequency; a code table storage in which a plurality of code sequences serving as a source for a pseudo-noise code is stored; an address controller which selects, according to the timing signal, a code sequence to be read, from among a plurality of code sequences; a partial code sequence extractor which extracts, as a partial code sequence, a code of a predetermined length, from the code sequence to be read; and a parallel-series convertor which outputs the partial code sequence one bit at a time, according to the clock signal.
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