发明名称 Testing method for a semiconductor integrated circuit device, semiconductor integrated circuit device and testing system
摘要 A method that divides semiconductor integrated circuit devices (corresponding to S1 and S2) into a plurality of groups and tests them simultaneously has the semiconductor integrated circuit devices operate with a clock signal (corresponding to CLK1 and CLK2) having a frequency different from that in other groups in at least one group. A test is performed without decreasing the number of chips tested at one time.
申请公布号 US2010315116(A1) 申请公布日期 2010.12.16
申请号 US20100801210 申请日期 2010.05.27
申请人 NEC ELECTRONICS CORPORATION 发明人 SEYA SHUNICHI
分类号 G01R31/26 主分类号 G01R31/26
代理机构 代理人
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