发明名称 |
METHOD FOR LOWERING POWER LOSS AND CIRCUIT |
摘要 |
<p>A method and circuit for suppressing a bias current and decreasing power consumption. A current suppression circuit is coupled to a circuit element, which is capable of conducting the bias current. Coupling the current suppression circuit to the circuit element forms a node. In one operating mode, the current suppression circuit applies a voltage to the node in response to a heavy load. In another operating mode, the current suppression circuit lowers the voltage at the node in response to a light load or no load. Lowering the voltage at the node decreases the flow of bias current through the circuit element thereby lowering power loss.</p> |
申请公布号 |
WO2010144085(A1) |
申请公布日期 |
2010.12.16 |
申请号 |
WO2009US46899 |
申请日期 |
2009.06.10 |
申请人 |
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC;BASSO, CHRISTOPHE;LOUVEL, JEAN-PAUL |
发明人 |
BASSO, CHRISTOPHE;LOUVEL, JEAN-PAUL |
分类号 |
H02M3/335 |
主分类号 |
H02M3/335 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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