发明名称 Multiplicative Division Circuit With Reduced Area
摘要 The technology is a division circuit with decreased circuit area. An embodiment includes an integrated circuit implementing multiplicative division of a dividend input and a divisor input. The integrated circuit includes a lookup table circuit and multiplier circuits. The lookup table circuit providing an approximation of a reciprocal of a divisor input. The multiplier circuits receive the approximation and refine a quotient output of the dividend input and a divisor input. At least one of the multiplier circuits is a squaring circuit implementing multiplication with a reduced number of intermediate partial products. The reduced number of intermediate partial products prevent the squaring circuit from multiplication of any two unequal numbers and limiting the squaring circuit to multiplication of a same number by the same number.
申请公布号 US2010318592(A1) 申请公布日期 2010.12.16
申请号 US20090488956 申请日期 2009.06.22
申请人 SYNOPSYS, INC. 发明人 HAN KYUNG-NAM;TENCA ALEXANDRE;TRAN DAVID;KELLY RICK
分类号 G06F7/52;G06F17/50 主分类号 G06F7/52
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