发明名称 WIRING FORMING METHOD AND SEMICONDUCTOR DEVICE
摘要 <p>A via opening section (26) is formed by etching a second interlayer insulating film (19A) portion exposed from the region where an opening section (21), which is in a hard mask film (18) and corresponds to a second-layer wiring pattern, and an opening section (23), which is in a third resist pattern (22) and corresponds to a first-layer wiring pattern, overlap each other.</p>
申请公布号 WO2010143245(A1) 申请公布日期 2010.12.16
申请号 WO2009JP07062 申请日期 2009.12.21
申请人 PANASONIC CORPORATION;MATSUDA, TAKASHI 发明人 MATSUDA, TAKASHI
分类号 H01L21/768;H01L21/3205;H01L21/82;H01L23/52 主分类号 H01L21/768
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