| 摘要 |
PROBLEM TO BE SOLVED: To provide a conversion circuit which suppresses influences caused by a relative error in a capacitance value of a capacitor, and to provide a pipelined A/D conversion circuit with the conversion circuit. SOLUTION: In a unit conversion circuit, a difference voltage between differential inputs is applied to a first capacitor CSF during a first period of time, the first capacitor CSF is connected between the input and output of an amplifier AMP during a second period of time, and a second capacitor CR is connected between a reference voltage corresponding to the differential inputs and the amplifier input. Even if a relative error is present between capacitors, an A/D conversion error can be suppressed. COPYRIGHT: (C)2011,JPO&INPIT |
