发明名称 OFFSET CANCELLATION CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To reduce an output offset generated by a reference voltage difference in the offset cancellation circuit of a Hall element and parasitic capacitance attached to the capacitive element of the offset cancellation circuit. <P>SOLUTION: In the offset cancellation circuit, when a voltage is applied from the outside so as to switch a current flowing to the Hall element 10, a plurality of capacitors C1 and C2 are each charged by the output voltage of the Hall element 10 in the respective states. To switching elements S11 and S12 connecting the plurality of capacitors C1 and C2 in parallel, dummy switching elements D1 and D2 to be ON/OFF controlled mutually exclusively with the switching elements S11 and S12 are connected, respectively. <P>COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2010283713(A) 申请公布日期 2010.12.16
申请号 JP20090136906 申请日期 2009.06.08
申请人 SANYO ELECTRIC CO LTD;SANYO SEMICONDUCTOR CO LTD 发明人 OGAWA TAKASHI
分类号 H03F3/34 主分类号 H03F3/34
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