| 摘要 |
PROBLEM TO BE SOLVED: To reduce an output offset generated by a reference voltage difference in the offset cancellation circuit of a Hall element and parasitic capacitance attached to the capacitive element of the offset cancellation circuit. SOLUTION: The offset cancellation circuit includes: switching elements S13-S16 to which a voltage is applied from the outside so as to switch a current flowing to the Hall element 10 and which are ON/OFF controlled so as to apply the output voltage of the Hall element 10 to one of capacitors C1 and C2 for each of the states; and switching elements S9-S12 and S19 which are ON/OFF controlled so as to output the output voltage corresponding to charges charged to the capacitors C1 and C2 in the state that the capacitors C1 and C2 are connected in parallel. Each of the capacitors C1 and C2 is configured such that the parasitic capacitance Cx is connected to one of both terminals, and in the state that the capacitors C1 and C2 are connected in parallel, a reference voltage Vref is applied to one output terminal, and the parasitic capacitance Cx is connected to the terminal side to which the reference voltage Vref is applied. COPYRIGHT: (C)2011,JPO&INPIT
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