发明名称 WIRING FORMING METHOD AND SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To form a fine via pattern while reducing the man-hours for pattern design, the number of sheets of use masks and the deviation of superposition. SOLUTION: A part of an interlayer insulating film 19A, which is exposed to an area wherein an opening 21 corresponding to a wiring pattern in the second layer of a hard mask film 18 and an opening 23 corresponding to a wiring pattern in the first layer of a third resist pattern 22 overlap, is etched to form via openings 26 and 27. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2010283288(A) 申请公布日期 2010.12.16
申请号 JP20090137532 申请日期 2009.06.08
申请人 PANASONIC CORP 发明人 MATSUDA KOJI
分类号 H01L21/768;H01L21/3205;H01L23/52 主分类号 H01L21/768
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