METHOD FOR REGULATING VOLTAGE CHARACTERISTICS OF A LATCH CIRCUIT, METHOD FOR REGULATING VOLTAGE CHARACTERISTICS OF A SEMICONDUCTOR DEVICE, AND REGULATOR OF VOLTAGE CHARACTERISTICS OF A LATCH CIRCUIT

摘要

A voltage (Vdd) is set to a level lower than the voltage during normal operation (step S100), whereafter voltages are applied to a point (Vdd) where the source voltage is applied, a point where the ground voltage is applied, the semiconductor substrate and the well, such that a relatively high voltage is applied between the gate of an on-state transistor and the semiconductor substrate, and between the gate and the well (steps S110, S120). By this means, the threshold voltage of the on-state transistor can be elevated, and the variation of the threshold voltages of the transistors configuring a memory cell having a latch circuit can be reduced, improving the voltage characteristics of the memory cell.