发明名称 |
COMBINED BYTE-PERMUTE AND BIT SHIFT UNIT |
摘要 |
A processor includes a decode unit and a byte permute unit. The byte permute unit receives an instruction from the decode unit. The byte permute unit determines whether the instruction corresponds to a shuffle instruction or a shift instruction. For a shuffle instruction, the byte permute unit uses a byte shuffler to perform a shuffle operation indicated by the instruction. For a shift instruction that indicates a shift magnitude, the byte permute unit uses the byte shuffler to byte-level shift a source operand corresponding to the instruction by an integer number of bytes. The byte permute unit also generates a sequence of output bits by bit-shifting the byte-level shifted source operand by a number of bits such that the sum of the number of bits and the integer number of bytes is equal to the shift magnitude.
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申请公布号 |
US2010318771(A1) |
申请公布日期 |
2010.12.16 |
申请号 |
US20090482974 |
申请日期 |
2009.06.11 |
申请人 |
SUDHAKAR RANGANATHAN;CHOY JONATHAN;SARMA DEBJIT DAS |
发明人 |
SUDHAKAR RANGANATHAN;CHOY JONATHAN;SARMA DEBJIT DAS |
分类号 |
G06F9/06;G06F9/302;G06F9/315 |
主分类号 |
G06F9/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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