发明名称
摘要 PROBLEM TO BE SOLVED: To provide a method for analyzing a defect of a multilayer wiring structure which analyzes a defective factor affecting the performance from many image data accumulated in each process and shows it. SOLUTION: The method includes a step that takes pictures of each process of circuit substrates 1a, 1b, and 1c and stores the images of each process 3a, 3b, and 3c into a memory means 5; a step that inspects the circuit substrate 8 and sorts a defective from a non-defective; and a step that takes each process image of a product judged to be a non-defective in inspection as an image of a non-defective and each process image of a product judged to be a defective as an image of a defective, produces a collection of non-defective images 11a, 11b, and 11c and a collection of defective images 12a, 12b, 12c for each manufacturing process, and stores them into the memory means 5. The image is extracted corresponding to the inspection result and observes it, thereby, the analysis of defective can be efficiently progressed. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP4599980(B2) 申请公布日期 2010.12.15
申请号 JP20040301577 申请日期 2004.10.15
申请人 发明人
分类号 G01N21/956;G06T1/00;G06T7/00;H05K3/00;H05K3/46 主分类号 G01N21/956
代理机构 代理人
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