| 摘要 |
<p>A cache controller that writes data to a cache memory, (111) comprises: a first buffer unit (102) that retains data flowing in from outside to be written to the cache memory (111); a second buffer unit (108) that has a plurality of divided areas, each of the divided areas respectively retaining a data piece to be currently written to the cache memory (111), among pieces of the data retained in the first buffer unit (102); a monitoring unit (106) that monitors the divided areas of the second buffer unit (108) and reports whether the second buffer unit (108) has an available divided area; and an input and output controller (105) that controls the first buffer unit (102) to output the data piece to be currently written to the cache memory (111) to the second buffer unit (108) when it is reported by the monitoring unit (106) that the second buffer unit (108) has an available divided area.</p> |
