| 摘要 |
A data processor includes a single-token-record memory, a sequence circuit, and a memory controller. The single-token-record memory has a plurality of first storage locations. The sequencer circuit is coupled to the single-token-record memory. The sequencer circuit, responsive to a request to place a token in a tail-end of a queue, either stores said token into one of the plurality of first storage locations if the single-token-record memory stores no greater than a predetermined number of tokens associated with the tail-end of the queue, or stores the token with at least one additional token and a pointer to a next storage location into one of a plurality of second storage locations otherwise. The memory controller is coupled to the sequencer circuit to store the token with the at least one additional token and the pointer in a location of a multi-token-record memory having the plurality of second storage locations.
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