| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a time digital converter for performing optimal value control of a time delay amount. <P>SOLUTION: The time digital converter includes: a delay circuit which has a plurality of delay stages for delaying a clock signal to be input into multistages, and of which at least one of the plurality of delay stages is a variable delay stage; a plurality of flip-flops provided with the same number as the delay stages of the delay circuit, and incorporate output of the delay stages corresponding in parallel in response to input of a reference signal; an edge detection circuit which detects one or both of rising and falling of each output of the plurality of flip-flops; a counter circuit which counts the number of edges detected by the edge detection circuit; and a control circuit which controls the delay amount of the variable delay stage according to the number of edges counted by the counter circuit. <P>COPYRIGHT: (C)2011,JPO&INPIT |
