发明名称 |
ARCHITECTURE FOR VERY HIGH-SPEED DECISION FEEDBACK SEQUENCE ESTIMATION |
摘要 |
A method for providing a next-cycle input sample from a decision feedback equalizer to a symbol decoder using look-ahead computations such that timing contention between the decision feedback equalizer and the symbol decoder is reduced. During a symbol period, a set of possible values is computed in the decision feedback equalizer and a set of path memory symbols is computed in the symbol decoder, the set of path memory symbols being based on a current input sample. During the same symbol period, one of the possible values is selected as the next-cycle input sample based on at least one of the next-cycle path memory symbols produced from the symbol decoder.
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申请公布号 |
US2010303144(A1) |
申请公布日期 |
2010.12.02 |
申请号 |
US20100816071 |
申请日期 |
2010.06.15 |
申请人 |
ABNOUS ARTHUR;MADISETTI AVANINDRA;LUTKEMEYER CHRISTIAN A J |
发明人 |
ABNOUS ARTHUR;MADISETTI AVANINDRA;LUTKEMEYER CHRISTIAN A.J. |
分类号 |
H04L27/01;H04L25/03;H04L25/497 |
主分类号 |
H04L27/01 |
代理机构 |
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