| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL frequency synthesizer capable of reducing a natural frequencyω<SB>n</SB>of a loop filter while suppressing increase of an area of a capacitive element of the loop filter. SOLUTION: In this PLL frequency synthesizer 1A, a loop is composed of a phase comparison unit 12, a gate unit 13, a charge pump 14, a capacitive element 15, a potential adjustment unit 16, a voltage-controlled oscillator 18 and a feedback frequency division unit 19. In the loop, the gate unit 13 and the charge pump 14 are arranged in parallel with the potential adjustment unit 16. A charge/discharge current Icp is input from the charge pump 14 to the capacitive element 15 to reduce the difference between the phase of a reference oscillation signal RCLK and that of a feedback oscillation signal PCLK input to the phase comparison unit 12, and the potential of a first end of the capacitive element 15 is adjusted by the potential adjustment unit 16. COPYRIGHT: (C)2011,JPO&INPIT
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