发明名称 Semiconductor package and stack package using the same
摘要 PURPOSE: A semiconductor package and a stacked package using the same are provided to minimize the length of exposed wirings by forming an insulation layer on the upper side of a scribe lane. CONSTITUTION: A semiconductor chip includes a part of a scribe lane(110b). A plurality of bonding pads(114) is formed on the upper side of the semiconductor chip. A first insulation layer(118) is formed on the semiconductor chip in order to expose the bonding pads. Wirings(120) are arranged on the first insulation layer and are connected to the bonding pads. A second insulation layer(122) exposes a part of the wirings. The edge of the second insulation layer is expanded to the scribe lane.
申请公布号 KR100997795(B1) 申请公布日期 2010.12.02
申请号 KR20080110455 申请日期 2008.11.07
申请人 发明人
分类号 H01L23/12;H01L23/28 主分类号 H01L23/12
代理机构 代理人
主权项
地址