| 摘要 |
<P>PROBLEM TO BE SOLVED: To solve the following problem in a conventional digital phase locked loop circuit: a stable phase synchronization loop cannot be formed. <P>SOLUTION: A digital phase locked loop circuit includes: first and second counters for counting first and second clock signals, respectively; a delay clock-generating circuit for generating first and second delay clock signals delaying the first clock signal; a sampling circuit for sampling a count value of the second counter by the first clock signal and the first and second delay clock signals; a selecting circuit for selecting one of the sampled count values according to a phase difference from a third clock signal obtained by frequency-dividing the first and second clock signals by a predetermined number, and the sampled count values; a phase error-calculating circuit for calculating the phase difference from the first and third clocks according to the count values selected by the first counter and the selecting circuit; and a digital control oscillator for outputting a second clock according to the result of the calculation of the phase error-calculating circuit. <P>COPYRIGHT: (C)2011,JPO&INPIT |
