发明名称 PLL CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a PLL circuit that can reduce a circuit area of a loop filter, stabilize an operation of a voltage controlled oscillator, and reduce noise sensitivity. <P>SOLUTION: The PLL circuit includes: first and second charge pump circuits 4 and 5 for controlling an output voltage according to an output signal of a phase comparator 3; a first filter 6 outputting a first voltage signal in which a predetermined frequency component is removed from a signal generated based on an output from the first charge pump circuit 4; a second filter 7 for inputting a current output from the second charge pump circuit 5 and outputting a predetermined constant voltage as a second voltage signal; a voltage control unit 30 for outputting a third voltage signal based on a comparison result between the first voltage signal from the first filter 6 and a reference voltage; and the voltage controlled oscillator 10 that receives low gain inputs for the first and second voltage signals and a high gain input for the third voltage signal to generate an oscillating frequency based on the first to third voltage signals. <P>COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2010273320(A) 申请公布日期 2010.12.02
申请号 JP20100010054 申请日期 2010.01.20
申请人 RENESAS ELECTRONICS CORP 发明人 HIRAI YOSHINORI
分类号 H03L7/093;H03L7/099 主分类号 H03L7/093
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