| 摘要 |
A method and apparatus are provided for executing instructions from a plurality of instruction threads on a multi-threaded processor. The instruction threads may each include instructions of different complexity. A plurality of pipelines for executing instructions are provided and an instruction scheduler determines on each clock cycle the pipelines upon which instructions will be executed. Some of the pipelines are configured to appear to the instruction threads as single pipelines but in fact include two pipeline paths, one for executed instructions of lower complexity and the other. The instruction scheduler determines on which of the two pipeline paths an instruction should execute. |
