| 摘要 |
The registered memory module allows asynchronous read and write operations when a PLL clock circuit in the registered memory module is being activated from a disabled status. When the PLL clock circuit is being activated it is bypassed using a logic circuit. After the PLL clock circuit is fully operational the bypass circuit is switched off and the memory module is operated in the synchronous mode. The registered memory module allows enabling or disabling of its clock circuit without any interruption of its operation other than changing to asynchronous mode thus preventing memory "black-outs" whilst the PLL circuit is activated. When the clock circuit in the registered memory module is disabled, the power consumption of the registered memory module can be reduced. The registered memory module is also allowed to enter or exit an asynchronous operation mode without entering or exiting a self-refresh or pre-charge power down operation mode of the registered memory module.
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