发明名称 |
Branch target address cache storing direct predictions |
摘要 |
In at least one embodiment, a processor includes at least one execution unit and instruction sequencing logic that fetches instructions for execution by the execution unit. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a branch target address cache (BTAC) having at least one direct entry providing storage for a direct branch target address prediction associating a first instruction fetch address with a branch target address to be used as a second instruction fetch address immediately after the first instruction fetch address and at least one indirect entry providing storage for an indirect branch target address prediction associating a third instruction fetch address with a branch target address to be used as a fourth instruction fetch address subsequent to both the third instruction fetch address and an intervening fifth instruction fetch address. |
申请公布号 |
US7844807(B2) |
申请公布日期 |
2010.11.30 |
申请号 |
US20080024197 |
申请日期 |
2008.02.01 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
LEVITAN DAVID S.;ZHANG LIXIN |
分类号 |
G06F9/35;G06F9/355;G06F9/40 |
主分类号 |
G06F9/35 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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