| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an oversampling circuit capable of highly accurately correcting a phase in such a way that mutual phase differences between multi-phase clocks used for an oversampling type CDR circuit become at equal intervals. <P>SOLUTION: The oversampling circuit includes: a multi-phase clock generating section 200 for generating a multi-phase clock; a phase control section 205 for detecting a phase difference between multi-phase clocks and generating a phase control signal based on a result of the detection; and a phase adjusting section 203 which has delay circuits as many as the number of multi-phase clocks and adjusts a pass time of a signal inputted to each delay element based on the phase control signal for multi-phase clocks to adjust the phase difference between multi-phase clocks. Each delay circuit 300 is composed of a plurality of inverters in different sizes connected in series and inverters connected on post-stages of the plurality of inverters, and the pass time is adjusted based on a product of output resistance of one inverter selected from among the plurality of inverters and input capacitance of an inverter connected on the post-stage of the selected inverter. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
