| 摘要 |
A circuit for a flat panel display, capable of displaying images, is provided. The circuit includes an image storage and processing block for the images to be displayed, a display and timing controller block controlling the display operation, an image pixel matrix containing a multitude of rows and columns arranged pixel elements. The circuit also includes one or more controlled row driver blocks, one or more controlled column driver blocks, and a pixel display operation for displaying pixel elements employing an advanced multi line addressing operation applied to a row and/or column drive activated pixel element display operation. The advanced multi line addressing operation signifies that during every operating sequence a decomposition operation of image data is taking place by analyzing image data from multiple lines for common contents by pixel data comparison, separating common parts of the image data into a multi line data domain and residual parts of the image data into a single line data domain thus allowing for a display of these two data domains in separately activated pixel element display operations.
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