| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a reset circuit which changes the delay time of a reset signal, and to provide a semiconductor integrated circuit for reset. <P>SOLUTION: The reset circuit equipped with a delay circuit (timer 12) having a plurality of counter circuits (counters C1-C3) for counting the clock signals is constituted so that the delay time of a reset signal indicating the reset release can be changed by changing the number of stages of the counter circuits for counting the clock signals according to the voltage applied to a predetermined external terminal (terminal P4). <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
