发明名称 |
ERASE OPERATION CONTROL SEQUENCING APPARATUS, SYSTEMS, AND METHODS |
摘要 |
Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.
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申请公布号 |
US2010296348(A1) |
申请公布日期 |
2010.11.25 |
申请号 |
US20100847744 |
申请日期 |
2010.07.30 |
申请人 |
YU XIAOJUN;HAN JIN-MAN;YIP AARON |
发明人 |
YU XIAOJUN;HAN JIN-MAN;YIP AARON |
分类号 |
G11C16/16 |
主分类号 |
G11C16/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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