发明名称 OPEN TEST CIRCUIT OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE EQUIPPED WITH OPEN TEST CIRCUIT
摘要 PROBLEM TO BE SOLVED: To perform an open test of a semiconductor chip without increasing the number of terminals. SOLUTION: The semiconductor device 100 includes a plurality of semiconductor chips 10A, 10B. Each of the semiconductor chips includes: an input-output terminal 12-A (12-B) connected to an independent pin CSa (CSb) that is independent for each of the semiconductor chips; input terminals 11-A0, 11-A1 (11-B0, 11-B1) connected to common connection pins P0, P1 that are common to the plurality of semiconductor chips; and open test circuits 20-A0, 20-A1 (20-B0, 20-B1) that are connected between the input-output terminal 12-A (12-B) and the input terminals 11-A0, 11-A1 (11-B0, 11-B1) respectively and that check presence or absence of a malfunction of the common connection pins P0, P1 or the semiconductor chips 10A (10B). COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2010266254(A) 申请公布日期 2010.11.25
申请号 JP20090116073 申请日期 2009.05.13
申请人 ELPIDA MEMORY INC 发明人 SUZUKI TOSHIYUKI
分类号 G01R31/28;H01L25/00 主分类号 G01R31/28
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