| 摘要 |
In a PLL frequency synthesizer, a loop is constituted by a phase comparison unit, a gate unit, a charge pump, a capacitive element, a potential adjustment unit, a voltage-controlled oscillator, and a feedback division unit. In this loop, the gate unit and the charge pump are provided in parallel with the potential adjustment unit. A charging/discharging current is input from the charge pump to the capacitive element and the potential of a first end of the capacitive element is adjusted by the potential adjustment unit, so that a phase difference between a reference oscillation signal and a feedback oscillation signal input to the phase comparison unit is small.
|
