发明名称 LDPC DECODING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To solve the problem of having to hold a large amount of memories for storing estimated posteriori probability data in parallel in order to increase a transfer speed in an LDPC (low density parity check code) decoding circuit. SOLUTION: A memory A and a memory B are memories that correspond to a column 901 in which 1 continuously exists in code parts of an inspection matrix, and are composed of high-speed memories or flip-flops to always receive access. A memory C is a memory corresponding to a column 902 in which 1 exists at random in code parts, and a memory D is a memory corresponding to a parity part 1003 in which 1 exists step-wise, each of them being configured by a normal memory. Thus, the number of used memories is reduced by taking into consideration the characteristic of the inspection matrix to devise a method for storing the estimated posteriori probability data. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2010268179(A) 申请公布日期 2010.11.25
申请号 JP20090117236 申请日期 2009.05.14
申请人 NEC ENGINEERING LTD 发明人 KAKIUCHI YOSHIHIKO
分类号 H03M13/19 主分类号 H03M13/19
代理机构 代理人
主权项
地址
您可能感兴趣的专利