| 摘要 |
A memory circuit, where data is read from and written to the memory cell in one clock cycle via a port without pre-charging the port between reading data from and writing data to the memory cell via the port in the one clock cycle, is described. In one aspect, an embodiment of the present invention provides a memory circuit with a write control switch that has a voltage drop of substantially zero volts. In another aspect, an embodiment of the present invention provides a memory circuit with a write driver that uses a complementary metal oxide semiconductor (“CMOS”) inverter whose P-channel MOS (“PMOS”) transistor size is approximately 0.5 times its N-channel MOS (“NMOS”) transistor size. In yet another aspect, an embodiment of the present invention provides a memory circuit with a latch-type read sense amplifier.
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