发明名称 SerDes double rate bitline with interlock to block precharge capture
摘要 An embodiment of the invention provides a method of separating an early clock pulse and a late clock pulse into two different latches, wherein the early clock pulse is generated through a bit line. In response to the early clock pulse rising, a first data waveform is sent to a fourth data waveform. In response to a third data waveform rising, an early precharge is turned off. In response to the turning off of the early precharge and in response to a fifth data waveform dropping, an eighth data waveform rises if the first data waveform has a value of 1. In response to a sixth data waveform rising, a first pulse latch is opened.
申请公布号 US7839715(B2) 申请公布日期 2010.11.23
申请号 US20080260376 申请日期 2008.10.29
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 CHANG LELAND;DITLOW GARY;MONTOYE ROBERT K.;STORINO SALVATORE N.
分类号 G11C8/00 主分类号 G11C8/00
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