| 摘要 |
PURPOSE: A power managed lock optimization is provided to efficiently manage locks in a system which includes a processor by supplying programmable timer in a wakeup section. CONSTITUTION: A processor(10A) executes a first instruction defined as ISA(Instruction Set Architecture). The first instruction instructs the processor to put the thread in a low power state. The processor brings the thread from the low power state in response to a pulse of received signal from a timer unit(12). When a send event message is received from another processor(10B), the processor gets out of the low power state. |
