发明名称 Methods of analyzing integrated circuit equivalency and manufacturing an integrated circuit
摘要 Methods of analyzing equivalency with respect to split and limited release lots of wafers of integrated circuits. One embodiment of the split-lot method includes: (1) dividing a set of data regarding the split lot into control and experimental subsets, (2) summarizing statistics regarding the set and the subsets to an experimental unit above a site level and (3) performing a two-way analysis of variance with respect to the statistics to determine the equivalency, using the set for one way of the analysis of variance and the subsets for another way of the analysis of variance. One embodiment of the limited-release method includes: (1) designating a set of data regarding a lot fabricated by a normative integrated circuit fabrication process as a control set, (2) designating a set of data regarding the limited release lot as an experimental set, (3) summarizing statistics regarding the control and experimental sets to an experimental unit above a site level and (4) performing a Kruskal-Wallace test with respect to the statistics to determine the equivalency.
申请公布号 US7840302(B2) 申请公布日期 2010.11.23
申请号 US20060424249 申请日期 2006.06.15
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 DOBSON JOEL L.
分类号 G06F19/00 主分类号 G06F19/00
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