| 摘要 |
This disclosure concerns a semiconductor memory device comprising: a memory cell array having memory cells arrayed two-dimensionally; word lines connected to the memory cells of rows of the memory cell array; bit lines connected to the memory cells of columns of the memory cell array; sense amplifiers connected to the bit lines, and detecting data stored in the memory cells; a test pad passing a predetermined reference current from a power source, and transmitting a reference voltage based on the reference current; and test circuits connected between the power source and the test pad and intervening between the power source and the bit lines, the test circuits passing test currents according to the reference voltage via the bit lines.
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