发明名称 |
Wake-and-Go Mechanism with System Bus Response |
摘要 |
A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data value at the target address indicates that an event for which a thread is waiting has occurred. In response to the comparison resulting in a determination that the event has not occurred, the wake-and-go engine populates a wake-and-go storage array with the target address and snooping the target address on the system bus without data exclusivity. In response to the comparison resulting in a determination that the event has occurred, the wake-and-go engine issues a load command on the system bus to read the data value from the target address with data exclusivity.
|
申请公布号 |
US2010293340(A1) |
申请公布日期 |
2010.11.18 |
申请号 |
US20080024204 |
申请日期 |
2008.02.01 |
申请人 |
ARIMILLI RAVI K;SHARMA SATYA P;SWANBERG RANDAL C |
发明人 |
ARIMILLI RAVI K.;SHARMA SATYA P.;SWANBERG RANDAL C. |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|