发明名称 |
SYSTEMS AND METHODS FOR A PHASE LOCKED LOOP BUILT IN SELF TEST |
摘要 |
<p>An apparatus configured for a phase locked loop (PLL) built in self test (BIST) jitter measurement is described. The apparatus includes a phase detector. The phase detector produces a digital signal that describes a comparison between a reference signal and a feedback signal. The apparatus also includes a BIST controller. The BIST controller accumulates the digital signal with successive digital signals. The apparatus also includes a communication pin. The communication pin sends the accumulated signal to automatic test equipment (ATE) that determines whether the PLL is operating correctly based on the accumulated signal.</p> |
申请公布号 |
WO2010132714(A1) |
申请公布日期 |
2010.11.18 |
申请号 |
WO2010US34803 |
申请日期 |
2010.05.13 |
申请人 |
QUALCOMM INCORPORATED;DASNURKAR, SACHIN D. |
发明人 |
DASNURKAR, SACHIN D. |
分类号 |
G01R31/30;G01R31/317 |
主分类号 |
G01R31/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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