摘要 |
Disclosed is a MOSFET (100) which is a semiconductor device that can be reduced in the on-resistance, while being suppressed in the occurrence of stacking faults due to a heat treatment during the device production process. The MOSFET (100) comprises a silicon carbide substrate (1), an active layer (7) that is formed from single crystal silicon carbide and arranged on one main surface of the silicon carbide substrate (1), a source contact electrode (92) that is arranged on the active layer (7), and a drain electrode (96) that is formed on the other main surface of the silicon carbide substrate (1). The silicon carbide substrate (1) contains a base layer (10) that is formed from silicon carbide and an SiC layer (20) that is formed from single crystal silicon carbide and arranged on the base layer (10). The impurity concentration of the base layer (10) is higher than 2 × 1019 cm-3, and the impurity concentration of the SiC layer (20) is higher than 5 × 1018 cm-3 but lower than 2 × 1019 cm-3.
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申请人 |
SUMITOMO ELECTRIC INDUSTRIES, LTD. |
发明人 |
WADA, KEIJI;HARADA, SHIN;MASUDA, TAKEYOSHI;HONAGA, MISAKO;SASAKI, MAKOTO;NISHIGUCHI, TARO;NAMIKAWA, YASUO;FUJIWARA, SHINSUKE |