发明名称 |
INTEGRATED CIRCUIT STRUCTURE |
摘要 |
PROBLEM TO BE SOLVED: To provide a memory architecture for reducing variation of a data-retention power supply voltage. SOLUTION: This integrated circuit structure includes an active power supply line and a data-retention power supply line. A memory macro is connected to the active power supply line and the data-retention power supply line. The memory macro includes a memory cell array and a switch. The switch is configured to switch a connection between connecting the memory cell array to the active power supply line and connecting the memory cell array to the data-retention power supply line. The data-retention power supply line is outside of the memory macro. COPYRIGHT: (C)2011,JPO&INPIT |
申请公布号 |
JP2010263194(A) |
申请公布日期 |
2010.11.18 |
申请号 |
JP20100086356 |
申请日期 |
2010.04.02 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD |
发明人 |
LEE CHENG HUNG;LIAO HUNG-JEN |
分类号 |
H01L21/8242;G11C11/413;H01L21/822;H01L27/04;H01L27/10;H01L27/108 |
主分类号 |
H01L21/8242 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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