| 摘要 |
A shift register including shift register units controlled by first and second clock signals for generating an output signal. For each unit, in an active period, the first driving device drives the first switch device to activate the output signal, and the second driving device provides a voltage signal according to the first clock signal to drive the first switch device to de-activate the output signal. When the first switch device de-activates the output signal, the second switch device provides the voltage signal to serve as the output signal according to the second clock signal. In the active period, the voltage signal has a low level, and the first and second clock signals are set as alternating-current signals and are opposite to each other. In a blanking period, the voltage signal has a high level, and each of the first and second clock signals is set as a direct-current signal.
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