发明名称 DESIGN SUPPORT DEVICE, DESIGN SUPPORT METHOD, AND DESIGN SUPPORT PROGRAM
摘要 PROBLEM TO BE SOLVED: To reduce power consumption while maintaining timing of an order cell to which timing driven arrangement is performed. SOLUTION: First, initial information is acquired (S1801). Next, the predetermined number of ROW area candidates are set in a cell arrangeable area in which the timing driven arrangement of the order cell is performed (S1802). Then, ranking processing is executed (S1803) to put priority of the ROW area candidates ri. After this, the number N of required ROW areas to be actually used for a chip is calculated (S1803). A ROW area is determined from among the ROW area candidates (S1805). Then, alignment processing of the order cell is executed (S1806). COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2010262572(A) 申请公布日期 2010.11.18
申请号 JP20090114487 申请日期 2009.05.11
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 HORIGUCHI KENICHI;NAGATANI SHUICHI;ABE DAIJI;HORI SHINICHIRO
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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