| 摘要 |
The arrangement (10) has an electrically conductive conduction structure, and a layer stack (26) arranged between the structure and a dielectric positioned at a side wall of the structure. The layer stack has two electrically conductive conduction layers with respective layer thickness. An electrically conductive interlayer has a layer thickness in a range from 2 angstrom to 30 angstrom and a higher electrical resistivity than one of the conduction layers. Another conduction layer is made from material different from the interlayer and has a lower electrical resistivity than the interlayer. An independent claim is also included for a method for electrolytic deposition of a copper-conduction structure in an integrated circuit arrangement. |
