| 摘要 |
A method for selecting gate sizes for a logic network of an integrated circuit, wherein the logic network is defined by a plurality of logic paths that includes nodes, gates and interconnect, includes assigning, at one or more computers, gate sizes to gates adjacent to timing path end nodes of the logic network, determining an n-tuple of performance/loading parameters for each of the assigned gate sizes based on gate and interconnect delay models, and determining whether two or more logic paths share a descendant gate. Two or more logic paths that share a descendent gate are coupled. The method also includes grouping the n-tuples of parameters of coupled logic paths into bins based on gate sizes of the shared descendent gate, recursively propagating, node by node, the bins of n-tuples of parameters along the coupled logic paths, detecting whether any of the bins of n-tuples of parameters are suboptimal for all of the coupled logic paths based on a comparison of the n-tuples of parameters in bin-pairs, and eliminating all n-tuples of parameters of the suboptimal bins along the coupled logic paths to prune gate sizes associated with the suboptimal bins.
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