| 摘要 |
A test pattern generating device generates a test pattern with respect to a semiconductor circuit having first and second common circuits and a non-common circuit other than the first and second common circuits, wherein each of the first and second common circuits has a scan chain for checking an operation of the circuit by applying a test pattern from the outside of the circuit. A set of scan chains and a set of assumed faults are created for each of the first and second common circuits. Any of the first and second common circuits is determined as the common circuit of a first test target. After the determined common circuit of the first test target is subjected to ATPG and detection of circuit fault, a test pattern generated in successful ATPG about the common circuit of the first test target is diverted to the common circuit determined as the second test target, and ATPG and detection of a circuit fault of the non-common circuit part is carried out.
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